Low bit-error rate (BER) data communication over a communication channel is considered an important requirement in many systems. In the case of memory devices and systems, fulfilling this requirement is increasingly difficult due to signaling and circuit limitations. In future memory devices and systems, scaling of interface circuitry to accommodate higher data rates may be restricted by transistor sensitivity and threshold limits. In addition, even when interconnect length and material properties are kept constant, higher data rates may increase the relative impact of inter-symbol interference due to higher losses at increased data rates. Developing circuits with jitter that scales proportionally with the increase in line rate is becoming increasingly difficult. Given constraints on interface overhead and latency, developing faster interfaces with a low BER may become more challenging and expensive.
Like reference numerals refer to corresponding parts throughout the drawings.